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Processing Instruction
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#	Item
321	Back end table for the Intel 8080 micro-processor Gerard Buskermolen ABSTRACT A back end is a part of the Amsterdam Compiler Kit (ACK). It translates EM, a family of intermediate languages, into the assembly language of Add to Reading List Source URL: tack.sourceforge.net Language: English - Date: 2011-02-11 16:00:24 Central processing unit Assembly languages Zilog Z80 Intel Instruction set architectures Addressing mode Stack machine Instruction set Processor register Computer architecture Computer hardware Computing
322	New 130nm Itanium® 2 Processors for 2003 Harry Muljono, Stefan Rusu, Brian Cherkauer, Jason Stinson Intel Corporation, Santa Clara, CA R Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:42:26 Central processing unit Instruction set architectures Itanium Montecito CPU cache Intel Core Multi-core processor Processor register Computer architecture Computer hardware Computing
323	Beyond Claims of Free Transistors and Abundant Instruction-Level Parallelism Michael D. Smith STANFORD UNIVERSITY Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:44:35 Computer engineering Parallel computing Superscalar Central processing unit Reduced instruction set computing Instruction-level parallelism Computing Computer architecture Classes of computers
324	Analysis of Compiled Code: A Prototype Formal Model R.D. Arthan Lemma 1 Ltd. 2nd Floor, 31A Chain Street, Reading UK Add to Reading List Source URL: www.lemma-one.com Language: English - Date: 2008-07-11 10:37:24 Central processing unit Instruction set Microprocessor MIX PDP-8 Computer architecture Computer hardware Electronic engineering
325	The Au1000 Internet Edge Processor: TM A High Performance, Low Power SOC The First Chip in a Family of Parts from Alchemy Semiconductor, Inc. Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:37:56 Central processing unit Computer memory Instruction set architectures Microprocessors CPU cache Cache MIPS architecture Microarchitecture Cell Computer architecture Computer hardware Computer engineering
326	Microsoft PowerPoint - ARMbasics4 Add to Reading List Source URL: www.ee.ic.ac.uk Language: English - Date: 2001-10-18 10:48:50 Instruction set architectures Central processing unit Classes of computers Assembly languages Instruction set Addressing mode ARM architecture Processor register Reduced instruction set computing Computer architecture Computing Computer engineering
327	The Alpha[removed]Microprocessor: Out-of-Order Execution at 600 Mhz R. E. Kessler COMPAQ Computer Corporation Shrewsbury, MA Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:48:29 Central processing unit CPU cache Cache Computer memory Instruction set architectures Alpha 21264 Branch predictor Out-of-order execution DEC Alpha Computer architecture Computer hardware Computer engineering
328	____________________________________________________________________ DUAL-USE LIST - CATEGORY 4 - COMPUTERS ____________________________________________________________________ _________________________________________ Add to Reading List Source URL: www.wassenaar.org Language: English - Date: 2015-03-25 12:20:54 Adjusted Peak Performance Digital signal processing 64-bit FLOPS Central processing unit Computer Instruction set Parallel computing Digital signal processor Computer architecture Computing Electronics
329	Intel C2000 Atom Microserver Power Efficient Processing for the Data Center Brad Burres, Johan van de Groenendaal, Jonathan Robinson, Ian Steiner Intel Corporation - Server Architecture Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2014-08-01 16:48:47 X86 architecture Parallel computing Microprocessors Instruction set architectures Intel Core Intel X86-64 Multi-core processor X86 Computer hardware Computing Computer architecture
330	IEEE TRANSACTIONS ON COMPUTERS, VOL. 47, NO. 12, DECEMBER[removed]Optimizing the Instruction Cache Performance of the Operating System Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-02-24 14:03:13 Computer memory Compiler optimizations Software optimization Programming language implementation CPU cache Central processing unit Cache Inline expansion Assembly language Computing Software engineering Computer programming

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